The goal of putting more and more devices into integrated circuits has been an important goal in semiconductor manufacturing from the very invention of the integrated circuit. Higher density circuits allow for the manufacture of ever more powerful devices while greatly reducing costs on a per transistor basis. The traditional configuration of circuit elements is to form them laterally on the surface of a semiconductor substrate. This provides ease of manufacturing and reduced complexity. However, currently, semiconductor design engineers are struggling with many limitations to lateral devices.
The greatest challenge is the limits of lithography. The layers of integrated circuits are fabricated by patterning various components using photolithography. In photolithography, a layer of photo-sensitive material called photoresist is coated onto the device. Then the photoresist is exposed a light pattern corresponding to the desired patterns in a particular layer. However, components in integrated circuits have become so small that their size is on the order of the wavelength of light used to expose the photoresist. While various techniques have been employed to push this limitation beyond all reasonable expectation, at some point, this physical limitation will become insurmountable.
To address this challenge, engineers have devised vertically oriented devices. These devices are complex to manufacture. However, they hold the promise of providing compact devices with the functionality of devices that consume much more semiconductor surface area, but without the need to pattern smaller features lithographically. One such vertical device is the vertical gate all-around (VGAA) or nanowire (NW) device.
Of note, prior VGAA or NW techniques provide a transistor of a specific conductivity type. In complementary metal-oxide-semiconductor (CMOS) technology, it is desirable to couple every nMOS transistor to a pMOS transistor. This minimizes off-state leakage in CMOS circuits. To achieve this using prior art VGAA techniques, separate n-channel and p-channel areas must be provided, thus occupying more integrated circuit surface area.